How Multi-Die Designs and AI Are Reshaping the Industry

The semiconductor industry is undergoing one of its most profound transformations in decades. Driven by the insatiable demand for compute power largely fueled by AI workloads, engineers are moving away from traditional monolithic chips and shifting toward complex multi-die designs. This shift brings a new set of challenges that conventional design and validation methods simply cannot handle.

In a recent episode of the Tech Transformed podcast, host Dana Gardner sat down with Shekhar Kapoor, Executive Director of Product Line Management at Synopsys, to explore how the growing complexity of semiconductors is changing the way engineers design and validate modern systems. From thermal management to AI-driven automation, the conversation reveals why the old way of building chips is no longer good enough and what the future looks like.

Multi-Die Design

Kapoor explains that the transition to multi-die design is no longer a matter of preference but a necessity. He attributes this shift to the relentless demand for greater compute capacity, driven largely by the rapid growth of AI.

Traditional monolithic chips are hitting hard limits. Reticle sizes are maxing out, and rising yield and cost challenges make it increasingly impractical to pack more functionality onto a single die. Multi-die designs solve this by disaggregating functionality across smaller dies, each targeting the most appropriate process technology, then integrating them into a unified, optimised package.

Leading AI systems already integrate multiple compute and I/O dies alongside large high-bandwidth memory (HBM) stacks, scaling to 3x–5x reticle-class designs and beyond. The design challenge is very different. As Kapoor puts it: "You're no longer optimising a single chip, you're optimizing a system of chips."

This requires system-level co-design from day one, spanning architecture, silicon, packaging, power delivery, and interconnect strategy simultaneously. Engineers must think in terms of System Technology Co-Optimisation (STCO), not just chip-level optimization. The design tools, methodologies, and team workflows all need to change. For engineers and technology leaders looking to explore these trade-offs, Synopsys has published a comprehensive eBook on accelerating multi-die design and innovation. 

Thermal Analysis and Multi-Physics Validation

Historically, thermal, power, and electromagnetic analyses were performed as downstream validation steps once the core design was complete. In a multi-die world, that approach is no longer viable.

"Thermal management is becoming the number one issue when designing these multi-die designs. It has to be managed across a range of scales, from transistor activity to package and board level," Kapoor says. 

The problem with late-stage validation is timing. By the time thermal or power integrity issues surface, the most critical decisions are already locked in floorplans, interconnect topologies established, and packaging assumptions embedded.. At that point, the only options are costly ECOs, excessive margining, or a full redesign. Industry estimates suggest over-design can lead to up to 30-35 per cent wasted silicon and hundreds of millions of dollars in optimisation loss.

The solution is a shift-left approach that embeds multiphysics analysis from the earliest stages of design. When thermal hotspots, voltage drop issues, and electromagnetic interactions are identified early, engineers can adjust partitioning and placement strategies before they become expensive problems.

This is the methodology detailed in the Synopsys ebook on Multiphysics Fusion for multi-die design, which covers how teams can build continuous multiphysics validation into their flows to avoid late-stage surprises and protect both performance and reliability. 

Multiphysics Fusion and AI-Driven Chip Design

To operationalise the shift-left methodology at scale, Synopsys has introduced the concept of Multiphysics Fusion. This is the native integration of AI-powered EDA technologies with ANSYS's gold-standard multiphysics sign-off analysis capabilities.

Within the 3DIC Compiler platform, this means unifying the implementation environment with RedHawk-SC, RedHawk-SC Electrothermal, and HFSS-IC technologies. This brings IR drop, thermal, signal, and power integrity analysis directly into the design loop. The result is greater predictability, tighter correlation between in-design analysis and sign-off, and significantly fewer design iterations.

The impact on design closure times has been substantial. According to Kapoor, teams using the Multiphysics Fusion solution have seen turnaround times shrink "from weeks to days, and in some cases even hours" even for large, high-performance multi-die designs.

AI amplifies these gains further. Synopsys employs AI in two primary ways: assistive automation through its 3DSO.ai technology, which integrates multiphysics feedback into the optimization loop in real time, and agentic workflow orchestration, which becomes increasingly critical as system complexity scales toward designs incorporating hundreds or even thousands of GPUs. As Kapoor notes, at that scale, "agentic workflows could help engineers converge faster" and manage trade-offs that would otherwise be intractable. If you would like to find out more about this, download the full eBook: Multiphysics Fusion Technology for Multi-Die Designs Explained from Synopsys, which expands on each of these themes with real-world examples, design methodologies, and guidance for implementation teams. You can also connect with Shekhar Kapoor on LinkedIn.

Takeaways

• Multi-die architectures and their drivers.
• Challenges of traditional monolithic chips.
• Importance of early multi-physics analysis.
• Multiphysics fusion and its benefits.
• AI's role in design automation.
• Reducing time-to-market through integrated platforms.
• System-level co-design.
• Thermal management in 3D IC stacking.
• Shift left approach in multi-physics validation.
• Future trends in semiconductor design.